1. Field of the Invention
This invention relates to a regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device.
The invention also concerns a method for improving the efficiency of the discharging phase of such memory cells.
More particularly, the invention relates to a regulating circuit which comprises: at least one switch connected between a programming voltage reference and a common line to the source terminals of the transistors which form said memory cells; and at least one discharge connection between said common line to the source terminals and a ground voltage reference.
2. Discussion of the Related Art
As is well known, a non-volatile memory cell comprises a MOS transistor having a "floating" gate terminal, that is a high DC impedance to all the other terminals of that cell and the circuit in which the cell is connected.
The cell also comprises a second electrode, called the control gate, which is driven by suitable control voltages. The other electrodes of the MOS transistor are standard drain, source, and body terminals.
By changing the value of the voltage applied to the control gate, the amount of the charge present on the floating gate can be varied. This allows the transistor to be set for two different logic states: a first state with a "high" threshold voltage and a second state with a "low" threshold voltage.
If an intermediate voltage between these two values is applied to the control gate, the transistor state can be "read", since the transistor would either have a low or a high impedance between its drain and source terminals, depending on the value of the threshold voltage. Thus, the transistor functions as a logic memory element.
In addition, since the floating gate has a high impedance to any other terminals of the cell, the charge stored in the transistor can be maintained for an indefinite time, even if the power supply is removed from the circuit in which it is connected. Thus, the cell has non-volatile memory characteristics.
The operation whereby a charge is stored on the floating gate is referred to as the cell "programming", whereas the operation which results in the charge being removed from the floating gate is referred to as the cell "erasing".
A non-volatile memory circuit integrated to a semiconductor usually comprises a very large number of cells arranged basically into a matrix having plural rows (word line) and columns (bit line). The cells from one word line have in common the line which drives their respective control gates. The cells from one bit line have in common their respective drain terminals.
It is a well recognized fact that in order to erase the contents of a given memory cell, the source terminal is to be brought to appropriate positive voltage values.
Specifically, the cell is erased by initially applying a very high (higher than 10 V) voltage to the source electrode. On completion of this phase, the source terminal is connected to a ground voltage reference. In this manner, all the voltage is discharged from said terminal.
In the matrix of an ordinary memory device, the lines which interconnect the source terminals (SOURCE) are laid, however, side-by-side with the gate terminal lines, i.e. the word lines (WL) of the matrix cells, as shown in FIG. 1, for example.
There exists, accordingly, a parasitic capacitive coupling (Cpar) between these lines. This coupling may cause the voltage of adjacent word lines to drop at the end of the erasing phase, that is when the voltage of the source terminal line is discharged at a very fast rate.
If the word line voltage drops to negative values, the junction diodes of the transistors comprising the memory cells become forward biased, which may erase or alter the contents of memory cells other than the selected ones.
The seriousness of such a potential mishap can be readily appreciated.
An object of the present invention is to provide a regulating circuit which can ensure a slow decrease of the source terminal voltage at the end of the erasing phase, to thereby control the effectuation of the memory matrix cell discharging operations and overcome the drawbacks with which prior approaches have been beset.